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19-2461; Rev 0; 5/02
KIT ATION EVALU ABLE AVAIL
Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs
General Description Features
o Provide Tracking of Two External Power Supplies During Power-Up and Power-Down o Compatible with a Wide Range of External Power Supplies Independent of Output Power o Bus Voltage Undervoltage Lockout Enables/ Disables CORE and I/O Supplies Together o Detect Short Circuit on VCORE and VI/O, Disable CORE and I/O Supplies in Either Case o Output Undervoltage Monitoring o POK Status (MAX5040) o Operating VCC Supply Voltage Range: 2.5V to 5.5V o I/O Voltage Range: VCORE to 4V o CORE Voltage Range: 0.8V to VI/O
MAX5039/MAX5040
The MAX5039/MAX5040 provide intelligent control to power systems where two supply voltages need tracking. These cases include PowerPC(R), DSP, and ASIC systems, which require a lower CORE voltage supply and a higher I/O voltage supply. The MAX5039/MAX5040 control the output voltage of the CORE and I/O supplies during power-up, powerdown, and brownout situations. They ensure that the two power supplies rise or fall at the same rate, limiting the voltage difference between the CORE and I/O supplies. This eliminates stresses on the processor. The MAX5039/MAX5040 shut down both the CORE and I/O supplies if either one is shorted or otherwise fails to come up. The MAX5040 provides a power-OK (POK) signal that signals the processor if the CORE supply, the I/O supply, and the system bus supply (VCC) are above their respective specified levels. The MAX5039/MAX5040 are targeted for nominal bus VCC voltages from 4V to 5.5V. The MAX5039/MAX5040 work with CORE voltages ranging from 800mV to about 3V (depending on the gate-to-source turn-on threshold of the external Nchannel MOSFET) and I/O voltages ranging from VCORE to 4V. The MAX5039/MAX5040 provide tracking control of the I/O and CORE voltages using a single external N-channel MOSFET connected across them. This MOSFET is not in series with the power paths and does not dissipate any additional power during normal system operation. The external MOSFET is only on for brief periods during power-up/power-down cycling so a low-cost, small-size MOSFET with a rating of 1/4th to 1/8th of the normal supply current is suitable. The MAX5039/MAX5040 are offered in space-saving 8-pin MAX and 10-pin MAX packages, respectively.
Ordering Information
PART MAX5039EUA-T MAX5040EUB-T TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 8 MAX 10 MAX
VCC
WITH MAX5039 OR MAX5040
I/O
Applications
PowerPC Systems Embedded DSPs and ASICs Embedded 16- and 32-Bit Controller Systems Telecom/Base Station/Networking
CORE
VCC I/O CORE
WITHOUT MAX5039 OR MAX5040
Power-On and Power-Off With and Without Voltage Tracking Typical Operating Circuit and Pin Configurations appear at end of data sheet. PowerPC is a registered trademark of IBM Corp. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs MAX5039/MAX5040
ABSOLUTE MAXIMUM RATINGS
(All Voltages Referenced to GND) VCC, NDRV, SDO, and POK ..................................-0.3V to +14V CORE_FB, UVLO, I/O_SENSE, I/O, CORE ..........-0.3V to +4.25V All Pins to VCC (except POK)............................................. +0.3V NDRV Continuous Current .................................................50mA Continuous Current, All Other Pins .....................................20mA Continuous Power Dissipation (TA = +70C) 8-Pin MAX (derate 4.5mW/C above +70C) .............362mW 10-Pin MAX (derate 5.6mW/C above +70C) ...........444mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V CC = 2.5V to 5.5V, V UVLO = 2V, V CORE = 1.8V, V I/O = 2.5V, V CORE_FB = 1V, V I/O_SENSE = 2V (MAX5040 only), TA = -40C to +85C, unless otherwise specified. Typical values are at VCC = 5V, TA = +25C.)
PARAMETER EXTERNAL SUPPLY CONDITIONS VCC VCC Supply Current Lowest VCC Where SDO Is Valid SDO Output Low Voltage at VCC = VCCLO VCC IC Turn-On Voltage Threshold (Note 3) CORE Voltage Range I/O Voltage Range VCORE VI/O VCC ICC VCCLO (Note 2) VUVLO = VCC = VCCLO, I SDO = 50A, measure V SDO (Note 2) VCC rising Hysteresis I/O and CORE valid, VCC = 5.5V (Notes 4, 5) I/O and CORE valid (Note 5) VCC > 4V I/O and CORE valid (Note 5), 2.5V VCC 4V VUVLO rising Hysteresis VUVLO = 2V 0.8 VCORE VCORE 2.43 0.05 VI/O 4.0 VCC V (Note 1) 2.5 1.3 5.5 2.25 0.9 0.4 2.5 V mA V V V V SYMBOL CONDITIONS MIN TYP MAX UNITS
USER-PROGRAMMABLE UNDERVOLTAGE LOCKOUT UVLO Trip Threshold UVLO Input Bias Current CORE AND I/O REGULATION CORE Feedback, CORE_FB, and Reference Voltage CORE Regulator Large-Signal Gain CORE Regulator Crossover Frequency VC_REF AV CORE_FB to NDRV CORE_FB to NDRV Pullup strength, VI/O = 1V, VCORE = 2V, INDRV = -10mA Pulldown strength, VI/O = 2V, VCORE = 1V, INDRV = 10mA I/O-CORE Comparator Trip Threshold (Note 6) VTH VCORE - VI/O, VI/O falling VCORE - VI/O, VI/O rising VCC 3V VCC 2.5V VCC 3V VCC 2.5V 60 -15 784 800 60 400 40 50 13 17 90 0 80 100 27 35 130 15 mV 816 mV dB kHz VUVCC 1.200 1.230 110 250 1.260 V mV nA
NDRV Output Resistance
2
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Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 2.5V to 5.5V, V UVLO = 2V, V CORE = 1.8V, V I/O = 2.5V, V CORE_FB = 1V, V I/O_SENSE = 2V (MAX5040 only), TA = -40C to +85C, unless otherwise specified. Typical values are at VCC = 5V, TA = +25C.)
PARAMETER CORE Pulldown Resistance MONITOR OUTPUTS SDO Output Low Voltage VOLSDO I SDO = 1.8mA, VUVLO = 1V, VCC = 2.5V I SDO = -1.0mA, VCC = 4V SDO Output High Voltage VOHSDO I SDO = -1.0mA, VCC = 2.5V I/O_SENSE Trip Threshold POK Output Low Voltage POK Leakage Current POK Glitch Rejection Time Fault Time I/O and CORE INPUTS I/O Input Bias Current CORE Input Bias Current I/O_SENSE Input Bias Current CORE_FB Input Bias Current VI/O = 1V VCORE = 1V VI/O_SENSE = 0.8V VCORE_FB = 1.2V 20 20 250 300 A A nA nA VI/O_REF VOLPOK ILPOK tPOK tFAULT VI/O_SENSE rising Hysteresis IPOK = 1.8mA VPOK = VCC (Note 7) (Note 8) 10 50 15 20 VCC 0.4V V VCC 0.55V 1.200 1.230 25 0.4 1.0 1.260 V mV V A s ms 0.4 V SYMBOL CONDITIONS VCORE = 1.8V, VUVLO = 1V, VCC = 2.5V MIN TYP 20 MAX 50 UNITS
MAX5039/MAX5040
Note 1: VCC slew-rate limited to 30V/s. Note 2: SDO automatically goes low when the UVLO pin drops below its threshold (or VCC drops below 2.5V). SDO remains low as VCC falls. For some VCC below VCCLO SDO may float. Note 3: This undervoltage lockout disables the MAX5039/MAX5040 at VCC voltages below which the device cannot effectively operate. When VCC drops below the threshold, SDO goes low, the bleeder turns off, and POK is high impedance. Note 4: In order to regulate correctly, VCC must be higher than VCORE plus the turn-on voltage of the external N-channel MOSFET. Note 5: I/O and CORE valid mean the voltages on these pins have settled within their target specifications for normal operation. Note 6: CORE and I/O supplies rise and fall rates must be limited to less than 6.6V/s. Note 7: POK does not deassert for glitches less than tPOK. Note 8: A fault condition is latched when either of the two following conditions maintains for longer than tFAULT: VCORE_FB < VC_REF (i.e., VCORE is less than its set point) VI/O < VCORE A FAULT condition forces SDO and POK (MAX5040 only) low. CORE discharges to GND through 20 while VCC > 2.5V. Cycle UVLO or VCC low, then high, to clear a FAULT.
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3
Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs MAX5039/MAX5040
Typical Operating Characteristics
(VCC = 5V, VCORE = 1.8V, VI/O = 3.3V, TA = +25C, unless otherwise specified.)
SYSTEM POWER-UP/POWER-DOWN (VI/O RISING BEFORE VCORE)
VCC NDRV SDO POK SDO AND POK 5V/div I/O I/O I/O AND CORE 1V/div I/O AND CORE 1V/div 5ms/div
MAX5039/40 toc01
SYSTEM POWER-UP/POWER-DOWN WITHOUT MAX5039/MAX5040 (VI/O RISING BEFORE VCORE)
MAX5039/40 toc02
VCC 5V/div NDRV 5V/div VCC
VCC 5V/div
CORE 5ms/div
CORE
CORE_FB REFERENCE (VC_REF) vs. VCC AND TEMPERATURE
MAX5039/40 toc03
CORE REGULATOR LOOP BODE PLOT (SEE FIGURE 9)
60 50 40 GAIN (dB) 30 20 10 PHASE
MAX5039/40 toc04
804 803 CORE_FB REFERENCE (mV) 802 801 800 799 798 797 796 2.5 3.5 VCC (V) 4.5 TA = -40C TA = +25C TA = +85C
VCC = 5V, VI/O = 3.3V, VCORE = 1.8V AT 1A
180 150 120 90 60 30 PHASE MARGIN (DEGREES)
0 -10 -20 5.5 100 1k
GAIN
0 -30 -60
10k
100k
FREQUENCY (Hz)
VSDO vs. ISDO(SINK) VCC = 2.5V
MAX5039/40 toc05
VSDO vs. ISDO(SINK) VCC = 0.9V
350 300 TA = +85C 250 VSDO (mV) 200 150 100 TA = -40C 50 0 TA = +25C
MAX5039/40 toc06
400 350 300 250 VSDO (mV) 200 TA = -40C 150 100 50 0 0 1 2 ISDO(SINK) (mA) 3 4 TA = +25C TA = +85C
400
0
0.1
0.2
0.3
0.4
0.5
0.6
ISDO(SINK) (mA)
4
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Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs
Typical Operating Characteristics (continued)
(VCC = 5V, VCORE = 1.8V, VI/O = 3.3V, TA = +25C, unless otherwise specified.)
VSDO vs.ISDO(SOURCE)
MAX5039/40 toc07
MAX5039/MAX5040
NDRV PULLDOWN STRENGTH
MAX5039/40 toc08
NDRV PULLUP STRENGTH
TA = -40C
MAX5039/40 toc09
5 VCC = 4.5V 4 TA = +85C VSDO (V) 3 VCC = 2.5V 2 TA = +85C 1 TA = +25C TA = -40C TA = +25C TA = -40C
500 450 400 350 VNDRV (mV) 300 250 200 150 100 50 TA = -40C TA = +25C TA = +85C VCC = 5V 0 4 8 12 16 TA = -40C VCC = 2.5V TA = +85C TA = +25C
6 5 4 VNDRV (V) 3 VCC = 2.5V 2 1 0 TA = +85C TA = +25C TA = -40C VCC = 5V
TA = +85C
TA = +25C
0 0 0.5 1.0 1.5 2.0 2.5 3.0 ISDO(SOURCE) (mA)
0
20
0
4
8
12
16
20
INDRV (mA)
INDRV (mA)
UVLO RISING THRESHOLD vs. VCC
MAX5039/40 toc10
UVLO HYSTERESIS vs. VCC
115 110 UVLO HYSTERESIS ( mV) TA = +85C TA = +25C VI/O_REF (V) 105
MAX5039/40 toc11
I/O_SENSE THRESHOLD (VI/O_REF) vs. VCC
1.238 1.237 1.236 1.235 1.234 1.233 1.232 1.231 TA = -40C TA = +25C TA = +85C
MAX5039/40 toc12
1.239
1.244 1.242 1.240 VUVCC (V) 1.238 1.236 1.234 1.232 1.230 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 TA = -40C TA = +25C TA = +85C
100
TA = -40C
95
90 5.5 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5
1.230 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5
I/O_SENSE HYSTERESIS vs. VCC
29 I/O_SENSE HYSTERESIS (mV) 28 27 26 25 24 23 22 21 20 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 TA = -40C TA = +25C TA = +85C
MAX5039/40 toc13
POK GLITCH REJECTION vs. VCC
MAX5039/40 toc14
30
49 48 GLITCH REJECTION TIME (s) 47 46 TA = +25C 45 44 43 2.5 3.0 3.5 4.0 VCC (V) TA = -40C 4.5 5.0
TA = +85C
5.5
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5
Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs MAX5039/MAX5040
Pin Description
PIN MAX5039 1 2 MAX5040 1 2 NAME SDO VCC FUNCTION Active-Low Shutdown Output. Connect SDO to active-low shutdown input of both CORE and I/O supplies. SDO is high when VUVLO VUVCC and VCC 2.5V and if there is no fault. Supply Voltage Input. Connect VCC to the supply voltage that powers the CORE and I/O supplies. Bypass VCC to GND with a 1F capacitor. User-Programmable Undervoltage Lockout. Connect to midpoint of the voltage-divider from VCC to GND. Set trip point below minimum VCC voltage. VUVLO VUVCC forces SDO and POK (MAX5040 only) low. Use UVLO as an active-low shutdown input to turn on/off the CORE and I/O supplies if desired. Ground
3
3
UVLO
4
4
GND
5
7
CORE Feedback Input. Connect CORE_FB to the midpoint of the voltage-divider from CORE to GND. The MAX5039/MAX5040 keep CORE_FB from dropping below VC_REF by controlling NDRV. Any time VCORE_FB falls below VC_REF, NDRV rises above ground to a voltage sufficient to maintain VCORE_FB = VC_REF. If VCORE_FB remains below VC_REF for longer than tFAULT, a latched FAULT is generated. During a FAULT, MAX5039/MAX5040 continue to CORE_FB regulate CORE_FB. Three things halt regulation of CORE_FB: * If VCC falls below 2.5V, NDRV goes to GND. * If I/O falls below CORE, NDRV goes to VCC. * If VCORE_FB rises above VC_REF, NDRV goes to GND. CORE CORE Supply Sense Input. Connect CORE to the core output voltage. If VCORE > VI/O, NDRV goes to VCC, POK (MAX5040 only) goes low. FAULT is latched if this condition lasts longer than tFAULT. A 20 bleeder discharges CORE to GND whenever SDO is low and VCC > 2.5V. I/O Supply Sense Input. Connect to I/O output voltage. If VCORE > VI/O, NDRV goes to VCC, POK (MAX5040 only) drives low. A FAULT is latched if this condition lasts longer than tFAULT. N-Channel MOSFET Gate Driver. Connect NDRV to the gate of the external N-channel MOSFET that shunts I/O to CORE.
6
8
7 8
9 10
I/O NDRV
--
5
I/O Feedback Input. Use a resistor-divider to divide VI/O and apply to this pin. When I/O_SENSE VI/O_SENSE VI/O_REF, POK drives low. I/O_SENSE can also be used to monitor any other voltage. Open-Drain Power-OK Output. POK drives low when any condition below is true: * VCC 2.5V * VUVLO VUVCC * VCORE_FB VC_REF * VI/O VCORE * VI/O_SENSE VI/O_REF * MAX5039/MAX5040 latches a FAULT
--
6
POK
6
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Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs
Performance During Typical Operation
Scope shots are of the MAX5040 EV kit. Figures 1 through 8 demonstrate system performance of the MAX5040 under various power-up, power-down, and fault conditions. In some cases (described in detail below), startup or shutdown of the I/O and CORE supplies were purposely delayed with respect to each other to simulate possible system operating conditions. In Figure 1 (with MAX5040), VCC ramps up slowly and the I/O supply comes up before the CORE supply. As soon as VCC rises above 2.5V (at about 7.5ms) NDRV goes to VCC shorting the I/O and CORE supplies together. When VCC rises above 4.5V (bringing VUVLO above VUVCC), SDO goes high enabling the I/O and CORE supplies. Although the CORE PWM supply turns on 5ms after the I/O PWM supply, both supply voltages come up together because NDRV is held at VCC, shorting the supplies together through the N-channel FET. The I/O supply supports both the I/O line and the CORE line. Once VCORE rises close to its set point, NDRV falls to around 2.8V to regulate VCORE at its set point. At around 22ms, the CORE supply comes up, NDRV goes to GND, and POK goes high. On power-down, when VCC drops low enough to bring VUVLO below VUVCC, SDO immediately falls, turning the I/O and CORE supplies off. Simultaneously, POK falls, indicating power-down to the processor. When the I/O voltage drops below the CORE voltage, NDRV goes to VCC (at around 36ms), shorting the supplies together. NDRV remains at VCC until VCC falls below 2.5V and then it returns to GND. In Figure 2 (without MAX5040), VCC ramps up slowly and the CORE and I/O supplies are turned on when VCC exceeds 2.5V. The I/O voltage comes up before the CORE voltage. There is a 3.3V difference between the I/O and CORE supplies for about 4ms before the CORE supply finally comes up. When V CC powers down, I/O remains high for about 10ms after CORE reaches GND. In Figure 3 (with MAX5040), VCC ramps up slowly and the CORE supply comes up before the I/O supply. As soon as VCC rises above 2.5V (at about 7.5ms), NDRV goes to VCC, shorting the I/O and CORE supplies together. When VCC rises above 4.5V (bringing VUVLO above VUVCC), SDO goes high, enabling the I/O and CORE supplies. Although the I/O PWM supply turns on 8ms after the CORE PWM supply, both supply voltages come up together because NDRV is held at VCC, shorting the supplies together through the N-channel FET. The CORE supply supports both the CORE line and the I/O line until the I/O supply comes up. At around 23ms, the I/O supply turns on, pulling the I/O voltage above the CORE voltage. At this point, the MAX5040 brings NDRV to GND and POK goes high. On power-down, when VCC drops low enough to bring VUVLO below VUVCC, SDO immediately falls, turning the I/O and CORE supplies off. Simultaneously POK falls, indicating power-down to the processor. When the CORE voltage drops below its regulation point, NDRV begins to regulate it (at around 30ms). When I/O falls below CORE, NDRV is pulled up to VCC to short the two supplies together. In Figure 4 (without MAX5040), VCC ramps up slowly and the CORE voltage comes up before the I/O voltage. It takes about 8ms before the I/O supply finally comes up above the CORE supply. When VCC powers down, the supplies do not turn off together. CORE remains high for around 14ms after I/O falls. In Figure 5 (with MAX5040), the system power-up is attempted with the CORE supply held in shutdown. As soon as VCC rises above 2.5V, NDRV goes to VCC, shorting the I/O and CORE supplies together. Next, when VCC rises above 4.5V (bringing VUVLO above VUVCC), SDO goes high, enabling the I/O and CORE supplies. Both supplies come up together because NDRV is high. Note that the CORE supply is still off; CORE is held up through the N-channel FET shunt. Once VCORE rises close to its set point, the linear regulator holds VCORE to its set point by regulating NDRV to around 2.8V. After 15ms of regulating CORE, the MAX5040 latches a fault. SDO goes low, NDRV goes to VCC, and both supplies power down together. POK remains low throughout because a valid operating state was not achieved. In Figure 6 (with MAX5040), VCC is set to 5V. Toggling UVLO from low to high controls system startup. While UVLO is low and the VCC is 5V, NDRV is high, causing the supplies to be shorted together. When UVLO goes high, SDO also goes high, turning on the CORE and I/O supplies (at around 3ms). In this example, the I/O supply comes up before the CORE supply. The MAX5040 regulates CORE by driving NDRV to about 2.8V until the CORE supply comes up (at around 7ms), then NDRV falls to GND and POK goes high. When UVLO is driven low, SDO goes low, disabling the CORE and I/O supplies. NDRV goes to V CC and both supplies power down together. In Figure 7 (with MAX5040), VCC is set to 5V. Toggling UVLO from low to high controls system startup. While UVLO is low and the VCC is 5V, NDRV is high, shorting the supplies together while they are both off. When UVLO does go high, SDO also goes high, turning on the CORE and I/O supplies (at around 8ms). In this example, the CORE supply comes up before the I/O
7
MAX5039/MAX5040
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Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs MAX5039/MAX5040
SYSTEM POWER-UP/POWER-DOWN (VI/O RISING BEFORE VCORE)
VCC NDRV SDO POK SDO AND POK 5V/div I/O I/O AND CORE 1V/div VCC 5V/div NDRV 5V/div VCC
SYSTEM POWER-UP/POWER-DOWN WITHOUT MAX5039/MAX5040 (VI/O RISING BEFORE VCORE)
VCC 5V/div
I/O
CORE 5ms/div
CORE 5ms/div
I/O AND CORE 1V/div
Figure 1. System Power-Up/Power-Down (VI/O Rising Before VCORE) SYSTEM POWER-UP/POWER-DOWN (VCORE RISING BEFORE VI/O)
VCC NDRV SDO POK SDO AND POK 5V/div VCC 5V/div NDRV 5V/div
Figure 2. System Power-Up/Power-Down Without MAX5039/ MAX5040 (VI/O Rising Before VCORE) SYSTEM POWER-UP/POWER-DOWN WITHOUT MAX5039/MAX5040 (VCORE RISING BEFORE VI/O)
VCC 5V/div VCC
I/O
I/O
CORE 5ms/div
I/O AND CORE 1V/div
CORE 5ms/div
I/O AND CORE 1V/div
Figure 3. System Power-Up/Power-Down (VCORE Rising Before VI/O)
Figure 4. System Power-Up/Power-Down Without MAX5039/ MAX5040 (VCORE Rising Before VI/O)
supply. The MAX5040 holds up I/O by driving NDRV to VCC (because the I/O voltage is less than the CORE voltage) until the I/O supply comes up (at around 16ms). At this point, NDRV goes to GND and POK goes high. UVLO is driven low (at around 22ms), causing SDO to go low, disabling the CORE and I/O supplies. The CORE supply powers down at about 23ms and NDRV goes to 2.8V to regulate the CORE supply until I/O falls. Then NDRV goes to VCC when the I/O voltage falls to the CORE voltage (at around 36ms). Figure 8 (with MAX5040) starts out with the supplies in their normal range. At 3ms, CORE is shorted to GND.
8
NDRV goes high, and POK goes low immediately. NDRV shorts the I/O supply to the CORE supply, bringing the supplies down together. After 15ms, the MAX5040 latches a fault and SDO goes low turning off the supplies.
Detailed Description
The MAX5039/MAX5040 voltage-tracking controllers limit the maximum differential voltage between two power supplies during power-up, power-down, and brownout conditions. The devices provide a shutdown output control signal, SDO, which is used to turn on
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Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs
and off the CORE and I/O power supplies. The MAX5039/MAX5040 monitor and compare the CORE and I/O voltages as follows. When the I/O voltage is greater than or equal to the CORE voltage, MAX5039/MAX5040 regulate the external N-channel MOSFET as a linear regulator by controlling NDRV. The linear regulator regulates the CORE voltage to the value set by the external resistor-divider connected from CORE to CORE_FB and GND (see Figures 9 and 10). If the CORE_FB voltage is far less than its regulation point, VC_REF (800mV), NDRV drives high to VCC, effectively shorting CORE and I/O together through the external MOSFET. If the CORE_FB voltage equals VC_REF, NDRV goes into regulation mode. If the CORE_FB voltage is higher than VC_REF, the linear regulator goes into standby mode and pulls NDRV low, turning off the external N-channel MOSFET. When the I/O voltage is lower than the CORE voltage by VTH (90mV), the MAX5039/MAX5040 turn the external Nchannel MOSFET on by driving NDRV high to VCC. Whenever SDO is high, the MAX5039/MAX5040 track the time that NDRV is in regulation mode or driven high. If NDRV is in regulation mode or driven high for longer than tFAULT (15ms), a fault occurs and SDO is pulled low.
MAX5039/MAX5040
SYSTEM FAULT STARTUP (CORE SUPPLY FAILS TO TURN ON)
NDRV VCC POK SDO VCC 5V/div NDRV 5V/div SDO 5V/div POK 5V/div
SYSTEM TURN-ON/TURN-OFF UNDER UVLO CONTROL (VI/O RISING BEFORE VCORE)
UVLO SDO POK UVLO 5V/div SDO 5V/div POK 5V/div NDRV I/O I/O AND CORE 2V/div 2ms/div I/O AND CORE 1V/div NDRV 5V/div
I/O
CORE 4ms/div
CORE
Figure 5. System Power-Up/Power-Down, Fault Startup (CORE Supply Fails to Turn On) SYSTEM TURN-ON/TURN-OFF UNDER UVLO CONTROL (VCORE RISING BEFORE VI/O)
UVLO SDO POK UVLO 5V/div SDO 5V/div POK 5V/div NDRV I/O NDRV 5V/div I/O AND CORE 1V/div
Figure 6. System Turn-On/Turn-Off Under UVLO Control (VI/O Rising Before VCORE)
SHORT-CIRCUIT RESPONSE (CORE SHORTENED TO GND)
NDRV SDO
NDRV 5V/div SDO 5V/div POK 5V/div
POK
I/O
CORE 2ms/div
CORE 5ms/div
I/O AND CORE 1V/div
Figure 7. System Turn-On/Turn-Off Under UVLO Control (VCORE Rising Before VI/O)
Figure 8. Short-Circuit Response (CORE Shorted to GND)
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9
Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs MAX5039/MAX5040
Functional Diagram
800mV CORE_FB R VCC R NDRV VCC
MAX5040
UVLO
1.23V 400mV FAULT GENERATOR
I/O
FAULT CORE 15ms TIMER SDO BLEED GND POK
I/O_SENSE
1.23V
10
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Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs MAX5039/MAX5040
VIN (5V) I/O POWER SUPPLY VI/O = 3.3V AT 2.0A I/O Q1 Si9428 SO-8 CI/O 100F
IN
OUT
SHDN
PowerPC/ DSP/ASIC
CORE
IN
CORE POWER SUPPLY
VCORE = 1.8V AT 2.0A OUT CCORE 100F R1 9.53k 1% R4 50
SHDN
SDO CIN 1F VCC R7 25.5k 1% UVLO R8 10k 1%
CORE
I/O NDRV
C2 1.5nF C1 100nF R3 10k R2 10k 1%
MAX5039
CORE_FB
GND
Figure 9. Typical Application Circuit for the MAX5039
Designing with MAX5039/MAX5040
The MAX5039/MAX5040 provide intelligent control to power systems where two power supplies need tracking. Follow the steps below for designing with the MAX5039/MAX5040: 1) Select an appropriate external N-channel MOSFET (see the N-Channel MOSFET Selection section). 2) Set the CORE regulation voltage (see the Programming the CORE Voltage section). 3) Set the UVLO voltage trip threshold (see the Programming UVLO Voltage section). 4) Compensate the CORE linear regulator loop (see the Linear Regulator Compensation section). 5) Set the POK voltage trip threshold (MAX5040 only, see the Programming I/O_SENSE Voltage section). Figures 9 and 10 show an application example.
ulators that supply the CORE and I/O voltages. Using this single control signal, the MAX5039/MAX5040 turn the CORE and I/O power supplies on and off together, minimizing the voltage differential between them. SDO is low when: * The voltage on the UVLO pin is below V UVCC (1.230V). * VCC is below the IC turn-on voltage threshold (2.43V). * A fault condition is detected. The MAX5039/MAX5040 prevent premature turn-on of the CORE and I/O power supplies during power-up by actively holding SDO low as soon as VCC rises above 0.9V, provided the condition for SDO to stay low is valid. NDRV NDRV controls the gate of the external N-channel MOSFET (which is connected between the I/O and CORE voltages), as needed, as long as VCC is within its operating range. NDRV is driven high to VCC when VI/O < VCORE. NDRV regulates the external MOSFET as a linear regulator when VI/O > VCORE and VCORE_FB < VC_REF. NDRV is driven low when VI/O > VCORE and VCORE_FB > VC_REF.
11
Functional Description
SDO SDO is the shutdown signal output. Connect SDO to the CORE and I/O power-supply shutdown pins. SDO allows the MAX5039/MAX5040 to control the turning on and off of the external switching regulators or linear reg-
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Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs MAX5039/MAX5040
VIN (5V) I/O POWER SUPPLY VI/O = 3.3V AT 2.0A I/O R5 13.3k 1% Q1 Si9428 SO-8 CI/O 100F
IN
OUT
SHDN
PowerPC/ DSP/ASIC
CORE
IN
CORE POWER SUPPLY
VCORE = 1.8V AT 2.0A OUT R6 10k 1% CORE I/O I/O_SENSE C2 1.5nF C1 100nF R3 10k R2 10k 1% CCORE 100F R1 9.53k 1% R4 50
SHDN
GPIO
SDO CIN 1F VCC R7 25.5k 1% UVLO R8 10k 1%
NDRV
MAX5040
CORE_FB
GND
POK
Figure 10. Typical Application Circuit for the MAX5040
UVLO UVLO is a user-programmable undervoltage lockout input. When the UVLO voltage is above VUVCC, the MAX5039/MAX5040 hold SDO high, given that VCC is within its operating range and there is no fault condition present. When the UVLO voltage falls below VUVCC, SDO is pulled low. Use a resistor-divider from the input of the CORE and I/O power supplies to UVLO to GND to set the undervoltage lockout (see the Typical Application Circuit). The MAX5039/MAX5040 keep the CORE and I/O power supplies off (through the SDO) until their input voltage is within its operating range. UVLO can be used to turn off the CORE and I/O power supplies through SDO. Pull the UVLO pin low with an open-collector driver to assert SDO, which turns off the power supplies. Active Bleeder The MAX5039/MAX5040 contain an internal 20 Nchannel MOSFET bleeder that connects CORE to ground. The bleeder turns on whenever the MAX5039/ MAX5040 hold SDO low and VCC is above the VCC IC turn-on voltage threshold (2.43V). This bleeder assists in discharging the output capacitor(s) during powerdown/brownout conditions. The MAX5039/MAX5040 maintain tight voltage tracking of the CORE and I/O
12
voltages, as long as VCC is within its operating voltage range. It is important to discharge the output capacitors to ground before VCC drops out of its range. Figure 11 illustrates a method to prolong V CC after a powerdown/brownout condition. The hold-up capacitor, CHD, holds the voltage at VCC up and provides the power to the MAX5039/MAX5040 to keep them in operation even after V IN has gone down.
Power-Up
The MAX5039/MAX5040 prevent premature turning on of the CORE and I/O power supplies during power-up by actively holding SDO low as soon as V CC rises above 0.9V, provided the condition for SDO to stay low is valid. The MAX5039/MAX5040 completely turn on and NDRV is operational when VCC rises above the VCC IC turn-on voltage threshold (2.43V). In this state, the MAX5039/MAX5040 maintain tight tracking of the CORE and I/O output voltages. The MAX5039/ MAX5040 continue to hold SDO low until the UVLO voltage rises above VUVCC (1.230V). Once the UVLO voltage rises above VUVCC, SDO goes high, enabling the CORE and I/O power supplies at the same time. Without voltage tracking, depending on the
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Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs
VIN
VCC CHD 10F MAX5039 MAX5040 UVLO
Figure 11. Circuit Prolongs VCC After a Brownout/Power-Down Condition
power supplies startup delay and/or soft-start timing, which are specific to each of the power supplies, CORE and I/O outputs may not rise at the same time or at the same rate. Output loading and capacitance further separate the two output's rise time. The MAX5039/MAX5040 help the system to overcome these differences and keeps CORE and I/O voltages tracking together by controlling NDRV, dynamically driving NDRV high, low, or in regulation mode, depending on the CORE and I/O voltage condition.
Without voltage tracking, depending on the output capacitance and loading, CORE and I/O voltages may not fall at the same rate. Similar to the power-up condition, the MAX5039/MAX5040 keep CORE and I/O voltages tracking together by controlling NDRV, dynamically driving NDRV high, low, or in regulation mode, depending on the CORE and I/O voltage condition. During power-down/brownout, VCC is dropping and the UVLO voltage is also dropping. When the UVLO voltage falls below VUVCC, SDO is pulled low, disabling the CORE and I/O power supplies. Similar to the shutdown condition, the MAX5039/MAX5040 keep CORE and I/O voltages together. It is important that VCC remains in its operating voltage range in order to keep the MAX5039/ MAX5040 operating to provide tracking until the output voltages have discharged to a safe level. Figure 11 illustrates a method to prolong V CC after a powerdown/brownout condition. The bleeder circuitry is helpful in this power-down/brownout condition because the bleeder helps speed up the discharge process.
MAX5039/MAX5040
FAULT Condition
While SDO is high, the MAX5039/MAX5040 keep track of the time NDRV is driven high or in regulation mode. In a typical system during power-up, power-down/ brownout, and normal operation, the time NDRV is driven high or in regulation mode should last for only a few milliseconds. If this time exceeds tFAULT (15ms), indicating an abnormal condition, a fault is generated. During a fault condition, SDO is driven low and NDRV continues its operation as described in the NDRV section. A fault condition is latched. To clear a fault, toggle VCC and/or UVLO to unlatch and restart the system.
Normal Operation
After the power-up period is over, CORE and I/O output voltages settle to their respective regulated values. The linear regulator formed by MAX5039/MAX5040 and the external MOSFET is turned off. During normal operation, the linear regulator goes into a standby mode and NDRV is driven low. The resistor-divider from CORE to CORE_FB to GND must be set so that the linear regulator regulation voltage is less than the CORE power-supply regulation voltage. See the Programming the CORE Voltage section. During normal operation, the MAX5039/MAX5040 constantly monitor the CORE, I/O, and CORE_FB voltages. NDRV responds as needed, according to the conditions described in the NDRV section.
Output Short-Circuit Condition
If any of the outputs are shorted to ground, NDRV is driven high to keep the CORE and I/O voltages tracking each other. The current through the external MOSFET is limited by the current limit provided by the external power supply. If the short-circuit condition lasts more than tFAULT, a fault is generated, SDO is driven low (which turns off the CORE and I/O power supplies), and NDRV continues its operation as described in the NDRV section.
Applications Information
N-Channel MOSFET Selection
The external N-channel MOSFET connected between CORE and I/O power supplies is expected to turn on briefly during power-up and power-down/brownout conditions. During normal operation, this MOSFET is turned off. In general, only a small size MOSFET is needed. A MOSFET capable of carrying 1/4th to 1/8th
13
Power-Down/Brownout or Shutdown
The MAX5039/MAX5040 continue to provide tracking for the CORE and I/O output voltages during powerdown/brownout or shutdown. During shutdown (UVLO is pulled below VUVCC), SDO is pulled low, disabling the CORE and I/O power supplies together. The CORE and I/O output voltages start to fall.
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Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs
of the maximum output current rating of the CORE or I/O power supplies is adequate. However, care should be taken when selecting this MOSFET to make sure it is capable of sustaining all of the worst-case conditions, as well as riding through all of the fault conditions. The following are guidelines for selecting the external Nchannel MOSFET: 1) MOSFET drain-to-source maximum voltage rating: VDS rating > VI/O maximum voltage. 2) MOSFET gate-to-source maximum voltage rating: VGS rating > VCC maximum. 3) MOSFET gate turn-on threshold voltage: VGS(th) < minimum operating voltage of (VCC - VCORE). For example, if VCC minimum operating voltage is 4.5V, CORE voltage is 1.8V, then VGS(th) < (4.5V - 1.8V) = 2.7V. A MOSFET with logic-level gate turn-on threshold voltage is appropriate for this application. 4) Determine the maximum current that can go through the MOSFET during power-up, powerdown/brownout, or output short-circuit conditions. In most cases, this maximum current is the current limit of the CORE or the I/O power supplies, whichever is larger. Choose the MOSFET with pulse current rating sufficiently higher than this current. Note that typical MOSFET pulse current rating is much larger than its continuous current rating. 5) Determine the MOSFET maximum RDSON such that under worst-case current, the voltage drop across its drain-to-source is within the tracking limit (approximately 400mV for most PowerPCs, ASICs, and DSPs). Determine the maximum single-shot power dissipation in the MOSFET during power-up, or during an output short-circuit condition. Considering the following cases: * When either the I/O or CORE is shorted to GND, NDRV is driven high to VCC, turning the MOSFET on. The current through the MOSFET is the maximum current that the supply not shorted can produce (the CORE supply maximum current if I/O is shorted or vice versa). Depending on which supply is shorted, take the maximum short-circuit current that either the I/O or CORE supplies produce. Call this current IPSLIM. In this case, the power dissipation in the MOSFET is IPSLIM2 x RDS(ON). * During power-up, the I/O voltage comes up first, and the CORE power supply fails to turn on. The MOSFET is in linear regulator mode, supporting the CORE full-load current, as 7) well as the charging of the CORE output capacitor. For most practical cases, the power charging the CORE output capacitor can be ignored. The power dissipation in the MOSFET for this case is (V I/O - V CORE ) x ICORE, where VI/O is the regulated I/O voltage, VCORE is the regulated CORE voltage, and ICORE is the CORE full-load current. * During power-up, the CORE voltage comes up first, and the I/O power supply fails to turn on. The MOSFET turns on hard, keeping the I/O voltage close to the CORE voltage. The MOSFET in this case supports the I/O load current, as well as the charging of the I/O output capacitor. For most practical cases, the power charging the I/O output capacitor can be ignored. Since the I/O voltage never reaches its final value, the I/O load current might be off and the power dissipation in the MOSFET is minimal. However, assuming the worst-case condition that the I/O load draws its full-load current, the power dissipation in the MOSFET would be II/O2 x RDS(ON), where II/O is the I/O full-load current. The worst-case single-shot power dissipation in the MOSFET is the maximum value from the steps above and for a maximum duration of tFAULT. Next, select the MOSFET that can take this single pulse energy without going over its maximum junction temperature rating. The maximum MOSFET junction temperature can be calculated as follows: TJ = TAMB + PPULSE x ZJA where TJ is the junction temperature, TAMB is the ambient temperature, PPULSE is the single-shot power dissipation calculated in step 6 above, and ZJA is the junction-to-ambient thermal impedance of the selected MOSFET for a single pulse of t FAULT duration. Z JA is specified in all typical MOSFET data sheets.
MAX5039/MAX5040
6)
Example: I/O = 3.3V, I/O power supply has a current limit (II/O(LIM)) of 6A, I/O full-load current is 3A. CORE is 1.8V, CORE power supply has a current limit (ICORE(LIM)) of 6A, CORE full-load current is 4A. VCC = 5V + 0.5V. CORE and I/O voltages must track to within 400mV. Choose a Si9428DY (N-channel MOSFET, VDS max = 20V, RDS(ON) at +25C = 0.04 at VGS = 2.5V, RDS(ON) at +125C = 1.5 x RDS(ON) at 25C, from the MOSFET data sheet, VGS max = 8V).
14
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Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs MAX5039/MAX5040
NORMALIZED THERMAL TRANSIENT IMPEDANCE, JUNCTION TO AMBIENT
2 1
NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE
DUTY CYCLE = 0.5
0.2 NOTES: 0.1 0.1 0.05 0.02 t1 t2 1. DUTY CYCLE, D = t1 t2 PDM
SINGLE PULSE 0.01 0.0001
2. PER UNIT BASE = RthJA = +70C/W 3. TJM - TA = PDMZthJA (t)
4. SURFACE MOUNTED 0.001 0.01 0.1 1 SQUARE WAVE PULSE DURATION (s) 10 100 600
Figure 12. Normalized Thermal Transient Impedance
From step 5: the maximum VI/O and VCORE differential voltage = (ICORE(LIM)) x (RDS(ON)) = 6A x 0.04 x 1.5 = 360mV. From step 6 (first bullet): power dissipation = IPSLIM2 x RDS(ON) = (6A)2 x 0.04 x 1.5 = 2.16W. From step 6 (second bullet): power dissipation = (VI/O VCORE) x ICORE = (3.3V - 1.8V) x 4A = 6W. From step 6 (third bullet): power dissipation = II/O2 x RDS(ON) = (3A)2 x 0.04 x 1.5 = 0.54W. So, the worst-case power dissipation in the MOSFET is 6W for a maximum duration of 20ms. From the Si9428DY data sheet, under the normalized thermal transient impedance curve (Figure 12), the ZJA is 0.05 x +70C/W for a single pulse. The worst-case junction temperature of the MOSFET at +85C ambient temperature is: TJ = TAMB + PPULSE x ZJA = +85C + 6W x 0.05 x +70C/W = +106C
To calculate the high-side limit, set the maximum CORE voltage set point at the minimum system CORE voltage minus the total system tolerance: CORESETMAX = COREMIN - TOL (TOL = Total Tolerance) Calculate the low-side constraint by taking the maximum system I/O voltage, subtracting the maximum allowable I/O to CORE difference and adding the total system tolerance. CORESETMIN = I/OMAX - VI/OC + TOL The following comprise the sources for the total system tolerance: * Resistor mismatch * MAX5039/MAX5040 reference error * Loop gain error For example: * VCORE = 1.800 5% * VI/O = 3.300 5% * Maximum voltage that I/O can exceed CORE without damage to the processor: VI/OC = (VI/O - VCORE)MAX = 2V * System gain = 200V/V
Programming the CORE Voltage
See the application circuit examples in Figures 9 and 10. The following explains constraints on the CORE voltage. The high-side constraint requires that the CORE regulator maintain a minimum voltage during normal operation. The low-side limit requires that the CORE regulator hold the CORE voltage such that the voltage difference from I/O to CORE does not exceed the processor's maximum allowable voltage difference:
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15
Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs MAX5039/MAX5040
Resistor mismatch: ERRORRES (%) = RES _ TOL x 2 x 1 - Ratio ; Ratio =
Table 1. Error Summation
ERROR Divider Mismatch (1% resistor) Reference Voltage Loop Gain Error Total = TOL AMOUNT (%) 1.0 2.0 0.5 3.5%
{(
)}
800mV VREGNOM
If the CORE set point is 1.6V, the ratio is 800mV/1600mV = 0.5. With 1% resistors, the resistor error is: ERRORRES(%) = 1% x {2 x (1 - 0.5)} = 1% MAX5039/MAX5040 reference error: 2.0%. Loop gain error: Loop gain error is due to the finite system gain. A loop gain of 200 yields a 0.5% gain error. Calculate the maximum and minimum regulator core voltage set point as follows: CORESETMAX = COREMIN - TOL = (1.8V - 5%) - 3.5% = 1.8V x 91.5% = 1.647V CORESETMIN = I/OMAX - VI/OC + TOL = ((3.3V + 5%) - 2V) + 3.5% = (3.465V - 2V) x 103.5% = 1.465V x 103.5% = 1.516V Set the CORE voltage set point (VREGNOM) between 1.516V and 1.647V and as close to the upper value (1.647V) as possible. Connect the midpoint of a voltage-divider between CORE and GND to CORE_FB, as shown in the Typical Application Circuit. Set the midpoint voltage to 800mV for a maximum CORE voltage set point of 1.647V. Choose a value for R2 of 10k. Calculate R1 with the following equation: V R1 = REGNOM - 1 R2 V C _ REF Example: V 1.647V R1 = REGNOM - 1 R2 = - 1 10k = 10.6k V 0.8V C _ REF Using a standard 10.0k (1%) resistor in series with a 604 (1%) resistor yields negligible resolution error.
mable UVLO feature allows VIN to get to a certain value before MAX5039/MAX5040 turn the system power supplies on together. VIN is usually the input voltage to the system power supplies and it can be the same as VCC. The UVLO pin also provides the system a way to turn on/off the system power supplies (see the UVLO section). Choose the UVLO trip point such that the minimum VIN voltage exceeds the maximum UVLO rising threshold. Follow the guidelines below to program the UVLO voltage: 1) Determine the VIN tolerance; 5% is common. 2) Determine the VUVLO rising threshold tolerance: Undervoltage lockout rising trip threshold, VUVCC, tolerance: 1.230V 2.5% Programming resistor tolerance: pick a 1% resistor or better (2% over temperature) Resistor-divider stack-up tolerance: 1% maximum for 1% resistors Resistor value resolution: 0.5% (can be zero if exact resistor value is available) Extra margin: 1% Total = 7% 3) Set VUVLO nominal value to: VIN nominal value - (VIN tolerance + VUVLO tolerance) 4) Calculate R7 using the equation: V R7 = UVLONOM - 1 R8 VUVCC where R8 is typically 10k. Example: VIN nominal value = 5V, VIN tolerance = 5%; set the VUVLO nominal value to 5V - (5% + 7%) = 4.4V. Choose R8 = 10.0k, 1%:
V 4.4V R7 = UVLONOM - 1 R8 = - 1 10k = 25.8k VUVCC 1.230V
Programming UVLO Voltage
See the application circuit examples in Figures 9 and 10. The MAX5039/MAX5040 provide a user-programmable undervoltage lockout feature through the UVLO pin. When using a resistor-divider, R7 and R8, from an input voltage rail (VIN) to UVLO to GND, the user-program16
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Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs
Linear Regulator Compensation
See the application circuit examples in Figures 9 and 10. The external MOSFET, together with the feedback resistor-divider, R1 and R2, from CORE to CORE_FB to GND, and NDRV form a linear regulator loop. This linear regulator should be compensated for stable operation. Note: The linear regulator spends most of its time in idle mode. It operates in transient mode and regulation mode only during system power-up/power-down, brownout, and occasional system load transient conditions. Loop stability applies when the linear regulator is in the regulation mode. Follow these simple guidelines to stabilize the linear loop: (see the Core Regulator Loop Bode Plot in the Typical Operating Characteristics). 1) Place C1, a 100nF, ceramic capacitor (X5R, X7R type or better) from NDRV to GND. 2) Select R1 and R2, a resistor-divider from CORE to CORE_FB to GND to set the linear regulator output regulation voltage (see the Programming Core Voltage section). 3) Place R3 and C2, an RC network from CORE_FB to NDRV. Set R3 = R1 and calculate C2 as follows: C2 = 1 2 x 10kHz x R3 In Figures 9 and 10, a resistor value of 50 is used for R4 for extra margin.
MAX5039/MAX5040
Programming I/O_SENSE Voltage (MAX5040 Only)
See the application circuit examples in Figures 9 and 10. I/O_SENSE is used to monitor the I/O output voltage or any other voltage. The result is reported by the POK output signal. Choose the I/O_SENSE trip point such that the minimum monitored voltage at I/O_SENSE exceeds the maximum I/O_SENSE rising threshold. Follow the guidelines below to program the I/O_SENSE voltage: 1) Determine the tolerance of the output voltage to be monitored, VO: 5% is common. 2) Determine VI/O_SENSE rising threshold tolerance: I/O sense trip-point threshold, VI/O_REF, tolerance: 1.230V 2.5% Programming resistor tolerance: pick 1% resistor or better (2% over temperature) Resistor-divider stackup tolerance: 1% maximum for 1% resistors Resistor value resolution: 0.5% (can be zero if exact resistor value is available) Extra margin: 1% Total = 7% 3) Set VI/O_SENSE rising nominal value to: VO nominal value - (VO tolerance + VI/O_SENSE tolerance). 4) Calculate using the following equation: V I / O _ SENSENOM R5 = - 1 R6 VI / O _ REF where R6 is typically 10k. Example: VI/O nominal value = 3.3V, set VI/O_SENSE nominal value to 3.3V - (5% + 7%) = 2.904V. Choose R6 = 10.0k, 1%: V I / O _ SENSENOM R5 = - 1 R6 VI / O _ REF 2.904V R5 = - 1 10k = 13.61k 1.230V
4) Place R4, a preload resistor from CORE to GND. Calculate R4 as follows: R4 gfs VCORE 2 x 250Hz x CCORE ID
where gfs is the transconductance of the external MOSFET, Q1, as specified in its data sheet and ID is the current where gfs is specified. R4 must be sized to properly handle its power dissipation. Example: CORE power supply = 1.8V, VREGNOM = 1.6V, C CORE = 100F, Q 1 = Si9428 (Vishay Siliconix): R1 = R2 = R3 = 10.0k, 1% 1 C2 = = 1.6nF 2 x x 10kHz x 10k
(
)
Use 1.5nF standard value. From the Si9428 data sheet, gfs = 24S at ID = 6A:
R4 gfs VCORE 2 x 250Hz x CCORE ID = 24S 1.6V 2 x 250Hz x 100F 6A = 78
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17
Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs MAX5039/MAX5040
Typical Operating Circuit
TOP VIEW
VIN I/O IN POWER OUT SUPPLY SHDN
Pin Configurations
VI/O
I/O
SDO
1
8 7
NDRV I/O CORE CORE_FB
PowerPC/ DSP/ASIC
VCORE CORE
VCC 2 UVLO 3
MAX5039
6 5
CORE IN POWER OUT SUPPLY SHDN
GND 4
SDO VCC
CORE I/O NDRV
MAX
SDO 1
MAX5039
UVLO GND CORE_FB
10 NDRV 9 I/O CORE CORE_FB POK
VCC UVLO GND I/O_SENSE
2 3 4 5
MAX5040
8 7 6
MAX
Chip Information
TRANSISTOR COUNT: 1272 PROCESS: BiCMOS
18
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Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
8LUMAXD.EPS
MAX5039/MAX5040
8
4X S
8
INCHES DIM A A1 A2 b c D e E H MIN 0.002 0.030 MAX 0.043 0.006 0.037
MILLIMETERS MAX MIN 0.05 0.75 1.10 0.15 0.95
y 0.500.1 0.60.1
E
H
1
0.60.1
1
D
L
S
BOTTOM VIEW
0.010 0.014 0.005 0.007 0.116 0.120 0.0256 BSC 0.116 0.120 0.188 0.198 0.016 0.026 6 0 0.0207 BSC
0.25 0.36 0.13 0.18 2.95 3.05 0.65 BSC 2.95 3.05 4.78 5.03 0.41 0.66 0 6 0.5250 BSC
TOP VIEW
A2
A1
A
e
c b L
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0036
J
1 1
______________________________________________________________________________________________________
19
Voltage-Tracking Controllers for PowerPC, DSPs, and ASICs MAX5039/MAX5040
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
10LUMAX.EPS
1 1
e
10
4X S
10
INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 D1 0.120 0.116 0.118 D2 0.114 E1 0.116 0.120 E2 0.114 0.118 H 0.187 0.199 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 2.89 3.00 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H y 0.500.1 0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b D1 A1
E2 c E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
I
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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